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hm62256b series 32,768-word 8-bit high speed cmos static ram ade-203-135d (z) rev. 4.0 nov. 29, 1995 description the hitachi hm62256b is a cmos static ram organized 32-kword 8-bit. it realizes higher performance and low power consumption by employing 0.8 m m hi-cmos process technology. the device, packaged in 8 14 mm tsop, 8 13.4 mm tsop with thickness of 1.2 mm, 450-mil sop (foot print pitch width), 600-mil plastic dip, or 300-mil plastic dip, is available for high density mounting. it offers low power standby power dissipation; therefore, it is suitable for battery back-up systems. features high speed fast access time: 45/55/70/85 ns (max) low power standby: 1.0 m w (typ) operation: 25 mw (typ) (f = 1 mhz) single 5 v supply completely static memory no clock or timing strobe required equal access and cycle times common data input and output three state output directly ttl compatible all inputs and outputs capability of battery back up operation
hm62256b series 2 ordering information type no. access time package hm62256blp-7 70 ns 600-mil 28-pin plastic dip (dp-28) hm62256blp-7sl 70 ns hm62256blsp-7 70 ns 300-mil 28-pin plastic dip (dp-28na) hm62256blsp-7sl 70 ns hm62256blfp-7t 70 ns 450-mil 28-pin plastic sop (fp-28da) hm62256blfp-4slt *1 hm62256blfp-5slt hm62256blfp-7slt 45 ns 55 ns 70 ns hm62256blfp-7ult 70 ns hm62256blt-8 85 ns 8 mm 14 mm 32-pin tsop (tfp-32da) hm62256blt-7sl 70 ns hm62256bltm-8 85 ns 8 mm 13.4 mm 28-pin tsop (tfp-28da) hm62256bltm-4sl *1 hm62256bltm-5sl hm62256bltm-7sl 45 ns 55 ns 70 ns hm62256bltm-7ul 70 ns note: 1. under development
hm62256b series 3 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss v we a13 a8 a9 a11 oe a10 cs i/o7 i/o6 i/o5 i/o4 i/o3 cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ss a10 cs nc i/o7 i/o6 i/o5 i/o4 i/o3 v i/o2 i/o1 i/o0 a0 nc a1 a2 oe a11 nc a9 a8 a13 we v a14 a12 a7 a6 a5 nc a4 a3 cc 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ss a10 cs i/o7 i/o6 i/o5 i/o4 i/o3 v i/o2 i/o1 i/o0 a0 a1 a2 oe a11 a9 a8 a13 we v a14 a12 a7 a6 a5 a4 a3 cc hm62256blp/blfp/blsp series hm62256blt series hm62256bltm series (top view) (top view) (top view) pin description symbol function a0 a14 address i/o0 i/o7 input/output cs chip select we write enable oe output enable nc no connection v cc power supply v ss ground
hm62256b series 4 block diagram ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? a12 a5 a3 (msb) (lsb) a14 a13 a4 a8 a7 a6 i/o0 i/o7 cs we oe a2 a1 a0 a10 a11 (lsb) (msb) a9 v v cc ss row decoder memory matrix 512 512 column i/o column decoder input data control timing pulse generator read/write control function table we cs oe mode v cc current i/o pin ref. cycle x h x not selected i sb , i sb1 high-z h l h output disable i cc high-z h l l read i cc dout read cycle (1) (3) l l h write i cc din write cycle (1) l l l write i cc din write cycle (2) note: x: h or l
hm62256b series 5 absolute maximum ratings parameter symbol value unit power supply voltage *1 v cc 0.5 to +7.0 v terminal voltage *1 v t 0.5* 2 to v cc + 0.3 *3 v power dissipation p t 1.0 w operating temperature topr 0 to + 70 c storage temperature tstg 55 to +125 c storage temperature under bias tbias 10 to +85 c notes: 1. relative to v ss 2. v t min: 3.0 v for pulse half-width 50 ns 3. maximum voltage is 7.0 v recommended dc operating conditions (ta = 0 to +70 c) parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v v ss 000v input high (logic 1) voltage v ih 2.2 v cc +0.3 v input low (logic 0) voltage v il 0.5 *1 0.8 v note: 1. v il min: 3.0 v for pulse half-width 50 ns
hm62256b series 6 dc characteristics (ta = 0 to +70 c, v cc = 5 v 10%, v ss = 0 v) parameter symbol min typ*1 max unit test conditions input leakage current |ili| 1 m a vin = v ss to v cc output leakage current |i lo | 1 m a cs = v ih or oe = v ih or we = v il, v ss v i/o v cc operating power supply current i cc 615ma cs = v il, others = v ih / v il i i/o = 0 ma average operating power supply current hm62256b-4 i cc1 70 ma min cycle, duty = 100 %, i i/o = 0 ma cs = v il, others = v ih / v il hm62256b-5 i cc1 60 hm62256b-7 i cc1 33 60 hm62256b-8 i cc1 29 50 i cc2 5 15 ma cycle time = 1 m s, i i/o = 0 ma cs = v il, v ih = v cc , v il = 0 standby power supply current i sb 0.3 2 ma cs = v ih i sb1 0.2 100 m a vin 3 0 v, cs 3 v cc 0.2 v, 0.2 *2 50 *2 0.2 *3 10 *3 output low voltage v ol 0.4 v i ol = 2.1 ma output high voltage v oh 2.4 vi oh = 1.0 ma notes: 1. typical values are at v cc = 5.0 v, ta = +25 c and not guaranteed. 2. this characteristics is guaranteed only for l-sl version. 3. this characteristics is guaranteed only for l-ul version. capacitance (ta = 25 c, f = 1.0 mhz) *1 parameter symbol min typ max unit test conditions input capacitance *1 cin 8 pf vin = 0 v input/output capacitance *1 c i/o 10 pf v i/o = 0 v note: 1. this parameter is sampled and not 100% tested.
hm62256b series 7 ac characteristics (ta = 0 to +70 c, v cc = 5 v 10%, unless otherwise noted.) test conditions input pulse levels: 0.8 v to 2.4 v input rise and fall times: 5 ns input and output timing reference level: 1.5 v output load: hm62256b-4: 1 ttl gate + c l (30 pf)(including scope & jig) hm62256b-5: 1 ttl gate + c l (50 pf)(including scope & jig) hm62256b-7/8: 1 ttl gate + c l (100 pf)(including scope & jig) read cycle hm62256b -4 -5 -7 -8 parameter symbol min max min max min max min max unit notes read cycle time t rc 45 55 70 85 ns address access time t aa 45 55 70 85 ns chip select access time t acs 45 55 70 85 ns output enable to output valid t oe 30 35 40 45 ns chip selection to output in low-z t clz 5 5 10 10 ns 2 output enable to output in low-z t olz 5 5 5 5 ns 2 chip deselection in to output in high-z t chz 0 20 0 20 0 25 0 30 ns 1, 2 output disable to output in high-z t ohz 0 20 0 20 0 25 0 30 ns 1, 2 output hold from address change t oh 5 5 5 10 ns notes: 1. t chz and t ohz defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. this parameter is sampled and not 100% tested.
hm62256b series 8 read timing waveform (1) ( we =v ih ) t t t t t rc aa acs oe olz t oh t ohz t chz valid data address cs oe dout high impedance valid address read timing waveform (2) ( we =v ih , cs =v il , oe =v il ) address t t rc t oh t oh valid data dout aa valid address
hm62256b series 9 read timing waveform (3) ( we =v ih , oe =v il ) *1 t acs dout note: 1. address must be valid prior to or simultaneously with cs going low. valid data t chz cs t clz high impedance
hm62256b series 10 write cycle hm62256b -4 -5 -7 -8 parameter symbol min max min max min max min max unit notes write cycle time t wc 45 55 70 85 ns chip selection to end of write t cw 35 40 60 75 ns 4 address setup time t as 0 0 0 0 ns 5 address valid to end of write t aw 35 40 60 75 ns write pulse width t wp 30 35 50 55 ns 3, 8 write recovery time t wr 0 0 0 0 ns 6 we to output in high-z t whz 0 20 0 20 0 25 0 40 ns 1, 2, 7 data to write time overlap t dw 20 25 30 35 ns data hold from write time t dh 0 0 0 0 ns output active from end of write t ow 5 5 5 5 ns 2 output disable to output in high-z t ohz 0 20 0 20 0 25 0 40 ns 1, 2, 7 notes: 1. t ohz and t whz are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. this parameter is sampled and not 100% tested. 3. a write occurs during the overlap (t wp ) of a low cs and a low we . a write begins at the later transition of cs going low or we going low. a write ends at the earlier transition of cs going high or we going high. t wp is measured from the beginning of write to the end of write. 4. t cw is measured from cs going low to the end of write. 5. t as is measured from the address valid to the beginning of write. 6. t wr is measured from the earlier of we or cs going high to the end of write cycle. 7. durng this period, i/o pins are in the output state so that the input signals of the opposite phase to the outputs must not be applied. 8. in the write cycle with oe low fixed, t wp must satisfy the following equation to avoid a problem of data bus contention, t wp 3 t whz max + t dw min.
hm62256b series 11 write timing waveform (1) ( oe clock) t wc t cw t wp t as t ohz t dw t dh t aw t wr *1 address oe cs we dout din valid data valid address high impedance high impedance if cs goes low simultaneously with we going low or after we going low, the outputs remain in the high impedance state. note: 1.
hm62256b series 12 write timing waveform (2) ( oe low fixed) ( oe = v il ) address we dout din t wc t cw t wp t whz t dw t dh *1 t as cs t aw *2 *4 *3 t oh t ow t wr valid data valid address high impedance notes: 1. if cs goes low simultaneously with we going low or after we going low, the outputs remain in the high impedance state. 2. dout is the same phase of the write data of this write cycle. 3. dout is the read data of next address. 4. if cs is low during this period, i/o pins are in the output state. therefore, the input signals of the opposite phase to the output must not be applied to them.
hm62256b series 13 low v cc data retention characteristics (ta = 0 to +70 c) parameter symbol min typ* 1 max unit test conditions *6 v cc for data retention v dr 2.0 5.5 v cs 3 v cc 0.2 v, vin 3 0 v data retention current i ccdr 0.05 30 *2 m av cc = 3.0 v, vin 3 0 v 0.05 10 *3 cs 3 v cc 0.2 v, 0.05 3 *4 chip deselect to data retention time t cdr 0 ns see retention waveform operation recovery time t r t rc *5 ns notes: 1. typical values are at v cc = 3.0 v, ta = 25 c and not guaranteed. 2. 10 m a max at ta = 0 to + 40 c. 3. this characteristics guaranteed for only l-sl version. 3 m a max at ta = 0 to +40 c. 4. this characteristics guaranteed for only l-ul version. 0.6 m a max at ta = 0 to +40 c. 5. t rc = read cycle time. 6. cs controls address buffer, we buffer, oe buffer, and din buffer. if cs controls data retention mode, other input levels (address, we , oe , i/o) can be in the high impedance state. low v cc data retention timing waveform v v cc cs data retention mode t r 4.5v dr 2.2v 0v cs > v - 0.2v cc cdr t
hm62256b series 14 package dimensions hm62256blp series (dp-28) unit: mm 0.51 min 2.54 min 0.25 + 0.11 ?0.05 2.54 ?0.25 0.48 ?0.10 0??15 15.24 1.20 35.60 36.50 max 13.40 14.60 max 1 14 15 28 5.70 max 1.90 max hm62256blsp series (dp-28na) unit: mm 2.54 min 5.08 max 2.54 ?0.25 0.48 ?0.10 0??15 0.25 + 0.11 ?0.05 36.0 37.32 max 1.3 7.1 7.37 max 1 28 15 14 7.62 0.51 min 2.2 max
hm62256b series 15 hm62256blfp series (fp-28da) unit: mm + 0.08 ?0.07 0.17 0.20 ?0.10 3.00 max 1.27 ?0.10 0.40 + 0.10 ?0.05 8.40 18.00 18.75 max 1.27 max 28 15 1 14 11.80 ?0.30 0 ?10 1.00 ?0.20 1.70 hm62256blt series (tfp-32da) unit: mm 0.08 m 0.50 8.00 8.20 max 0.20 ?0.10 14.00 ?0.20 1.20 max 12.40 32 116 17 0.17 ?0.05 0.13 ?0.05 0 ?5 0.45 max 0.10 0.50 ?0.10 0.80

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